Design Verification Overview
Hidden
Specification analysis
Test plan creation
Testbench creation
Conduct verification
Coverage analysis
Hidden
Test writing
Running simulation
Bug detection
Regression test
Design Verification Capability
We have capability of design several types of library and IP
IP/SoC level Design Verification
Function level simulation
Selective test Pre-GLS level sim
Test environment for Post-GLS level sim
Coverage Driven Verification
Toggle/Code/Function Coverage metrics.
Verification Environment with UVM.
IP Verification of SoC.
USB2.0, USB3.0.
PCIE.
APB/AXI/AHB AMBA.
I2C/I3C.
DSI/CSI2.
UniPro/UFS.
VByOne IP.
PHY interface for PCIe Gen4.
DFT compiler.
ADC IP.