We provide design services across a wide range of application domains, supporting everything from legacy technologies to the latest advanced process nodes, covering the entire flow from synthesis to GDS out.
We enhance the competitiveness of our customers' products by leveraging a differentiated design flow that encompasses spec hand-off, integration, physical impementation, and comprehensive verification.
Design Service Flow
VNCHIP Technology provides RTL-to-GDSII, NETLIST-to-GDSII design services. VNCHIP Technology boasts a proven business track record and extensive engineering expertise, with over 200 successful designs. Our cutting-edge experience spans advanced 7nm, 6nm, and 3nm technologies, delivering solutions for automotive, AI, and HPC applications
RTL or NETLIST
A hand-off in the design flow transfers information from system designers to physical implementation designers.
It includes design rule checks and analysis of timing, signal integrity, and thermal issues
The implementation team handles RTL/netlist checks, scan insertion, placement, routing, and error corrections, delivering the final design file for fabrication.
Logic Synthesis & Logic Equivalent check
Sanity checks: library check, Netlist check, timing constraint check.
Early engagement
Performance, power, and area optimization by applying physical aware methodology
Equivalent check.
Low Power Solution
DFT
Scan design and ATPG
Memory BIST
At-speed test strategy
DFT constraints development
APR
Early Engagement
PowerPlan and FloorPlan
Chip size optimization
Clock Tree Synthesis
Custom CTS (H-TREE / SPINE)
Timing Optimization
Power, SI and Timing aware implementation
Signoff & Tapeout
Hierachical Timing Sign-off
Chiptop / Subsystem Timing Sign-off
Signal Integrity Sign-off
Power Integrity Sign-off
Physical Verification