Synthesis, LEC debug

· Sanity checks: library check, Netlist check, Timing constraints check

· Performance, Power, and Area optimization by applying physical aware methodology.

· Equivalent Check

Design For Testability

· Scan Design and ATPG

· Memory BIST

· At-Speed Test Strategy

· DFT constraints development

Place and Route

· FloorPlan/Power Planning

· Chip size optimization

· Clock Tree Synthesis

· Auto Place and Route

· PPA optimization

STA – Timing Closure

· SDC developing

· Hierarchical module signoff timing verification

· Chip top/Top block signoff timing verification

· Placement guideline for P&R

· Clock Specification for P&R

Physical Verification – DRC/LVS/ANT/DFM/ERC

· Design Rule Check

· Multi-Power LVS

· Crosstalk Analysis

· Electron Migration and IR-Drop analysis

· Antenna, DFM and ERC check.

· RDL custom route for Analog IPs

Tapped Out ASIC/SOC from 90nm down to 7nm FinFET process.

Experience on Low Power Design.

TSMC, GlobalFoundries, Samsung, UMC, SMIC

Synthesis: Design Compiler, Genus

PnR: ICC2, Innovus

RC Extraction: StarRC, QRC

Timing verification: PrimeTime, Tempus

Logic verification: Formality, Conformal

Multi voltage rule check: MVRC, VCLP

Power verification: PrimeRail, Voltus, RedHawk, SeaHawk

Physical verification: ICV, Calibre